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You are best equipped for this task if you have:

  • Masters/Bachelors in Electrical Engineering or Computer Science with 8-12 years of relevant work experience.

  • Strong foundational knowledge of digital design & verification.

  • Advanced knowledge and hands-on experience of System Verilog and UVM.

  • Hands-on experience in hardware-software debugging at the system or application level. Hand-on experience with gate-level-simulations and with debugging/troubleshooting skills.

  • Exposure to version-controlling (eg, Git/Bitbucket, Clearcase, CVS, SVN) and bug-management schemes.

  • Dynamic and energetic with zero verification escape mindset.

  • Self-motivated, flexible, good communication with interpersonal skills and is a good team player who is able to work well with both internal and external partners.

  • Candidate has proven ability to achieve results in a very dynamic, multi-site environment and be able to coordinate with priorities and self-initiatives.

  • Candidate must have high-speed communication peripherals (eg: PCIE, GETH) design and verification knowledge.

  • Experience in the automotive industry in functional safety and cybersecurity are advantageous.

  • Verification experience in high-speed IO or CPU peripherals and pattern development is a plus.

  • Candidate who has more relevant working experience will be considered for a more senior position.

Mô tả công việc

Job description

In your new role you will:

  • Undertake a technical leadership position in Digital Verification at SOC.

  • Execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements.

  • Write verification plans to meet these requirements after close alignment with other verification teams for proper work split according to mutually acceptable verification assignment.

  • Execute the verification plan by developing C/C++ test cases and System Verilog/UVM testbench components and by integrating 3rd party VIP components.

  • Simulate and debug at RTL, Unit Delay, and Gate Level using appropriate tools and flows including Emulator, Portable Stimulus, or Formal methodologies for functional and toggle coverage closure.

  • Leading a team technically through exploring new environments and identifying potential enhancement areas through the new methodology.

  • Identify and setting mid/long-term goals based on benchmarking against industry standards.

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