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Skills required

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You are best equipped for this task if you have:

  • Masters/Bachelors in Electrical Engineering or Computer Science with 8-12 years of relevant work experience.

  • Strong understanding of Analog/Mixed Signal circuits.

  • Understand the usage of tools like Virtuoso, Xcelium, Simvision and Waveview.

  • Hands-on experience in writing Verilog-A/MS and Real Number Models and building SPICE test benches at Block and Fullchip Level.

  • Hand-on experience in building the COSIM/ Mixed-signal verification environment.

  • Implement mixed-signal test-benches in Cadence Virtuoso and/or Verilog-AMS/System Verilog to apply stimulus and checks.

  • Hand-on experience with gate-level-simulations and with debugging/trouble shooting skills.

  • Exposure to version-controlling (eg, Git/Bitbucket, Clearcase, CVS, SVN) and bug-management schemes.

  • Experience in UVM-AMS is a plus.

  • Self-motivated, flexible and with strong interpersonal skills.

  • Good communication with interpersonal skills and is a good team player who is able to work well with both internal and external partners.

  • Candidate must have proven ability to achieve results in a very dynamic, multi-site environment and be able to co-ordinate with priorities and self-initiatives.

  • Experience in automotive industry in functional safety and cybersecurity are advantageous.

  • A candidate who have more relevant working experience will be considered for a more senior position. 

What you will do

At a glance

  • Are you looking for a new challenge? This job offers the opportunity to bring in your SoC Analog Mixed Signal Verification knowledge and develop your technical and personal skills in a growing, fast-paced and motivated team.

Job description

In your new role you will:

  • Undertake a technical leadership position in Digital and Analog-Mixed Signal Verification at SOC.

  • Execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements.

  • Write verification plans to meet these requirements after close alignment with other verification teams for proper work split according to mutually acceptable verification assignment.

  • Execute the verification plan by developing C/C++ testcases and System Verilog/UVM testbench components and by integrating 3rd part VIP components.

  • Leading a team technically through exploring new environments and identifying potential enhancement areas through new methodology.

  • Identify and setting mid/long term goals based on benchmarking against industry standards.

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